This invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a plurality of low resistance conductive layers to achieve a high speed operation.
A conventional semiconductor memory device has a plurality of memory cell arrays. Each memory cell array needs a decoder circuit, an equalizing control circuit and a transfer gate control circuit. Output signals of such circuits are transferred to gates of transistors of the memory cell arrays. If the output signals have a timing skew, the semiconductor memory device does not operate with high speed. Therefore, the conventional semiconductor memory device has a plurality of equalizing control circuits and transfer gate control circuits.